US 11,728,215 B2
Fin Field-Effect Transistor device and method of forming the same
Shich-Chang Suen, Hsinchu (TW); Kei-Wei Chen, Tainan (TW); and Liang-Guang Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 28, 2021, as Appl. No. 17/333,090.
Application 17/333,090 is a continuation of application No. 16/701,326, filed on Dec. 3, 2019, granted, now 11,024,540.
Application 16/701,326 is a continuation of application No. 16/104,006, filed on Aug. 16, 2018, granted, now 10,504,782, issued on Dec. 10, 2019.
Claims priority of provisional application 62/565,822, filed on Sep. 29, 2017.
Prior Publication US 2021/0296173 A1, Sep. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/70 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/285 (2006.01); H01L 21/033 (2006.01); H01L 29/78 (2006.01); H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/8238 (2006.01); H01L 21/3213 (2006.01); H01L 21/32 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02211 (2013.01); H01L 21/02227 (2013.01); H01L 21/02271 (2013.01); H01L 21/02301 (2013.01); H01L 21/02312 (2013.01); H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28525 (2013.01); H01L 21/28568 (2013.01); H01L 21/3105 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 21/823821 (2013.01); H01L 23/5226 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/32 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a gate structure over a substrate, wherein the gate structure is surrounded by a first dielectric layer;
forming a mask structure over the gate structure and over the first dielectric layer, wherein the mask structure comprises a dielectric structure over the gate structure and over gate spacers of the gate structure, and a second dielectric layer over the first dielectric layer around the dielectric structure;
forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the second dielectric layer and a portion of the dielectric structure;
removing the exposed portion of the second dielectric layer and a portion of the first dielectric layer underlying the exposed portion of the second dielectric layer, thereby forming a recess exposing a source/drain region adjacent to the gate structure; and
filling the recess with a conductive material.