US 11,728,167 B2
Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device
Dongjun Lee, Anyang-si (KR); Keunnam Kim, Yongin-si (KR); Daehyoun Kim, Hwaseong-si (KR); Taejin Park, Yongin-si (KR); and Sunghee Han, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 25, 2022, as Appl. No. 17/680,996.
Application 17/680,996 is a continuation of application No. 16/776,948, filed on Jan. 30, 2020, granted, now 11,270,885.
Claims priority of application No. 10-2019-0076683 (KR), filed on Jun. 26, 2019.
Prior Publication US 2022/0293420 A1, Sep. 15, 2022
Int. Cl. H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/0337 (2013.01) [H01L 21/0273 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a first area and a second area;
forming a hardmask structure comprising a plurality of hardmask layers on the target layer in the first area and the second area;
forming a photoresist layer on the hardmask structure in the first area and the second area;
forming a photoresist pattern by exposing and developing the photoresist layer in the first area and the second area;
forming a first hard mask pattern including a plurality of openings in the first area and the second area by transferring a shape of the photoresist pattern onto a first hardmask layer that is one of the plurality of hardmask layers, the first hardmask pattern comprising a negative hardmask pattern in the first area and a first positive hardmask pattern in the second area;
forming a second positive hardmask pattern in the first area by filling openings of the negative hardmask pattern in the first area with a second positive hardmask pattern material;
removing the negative hardmask pattern in the first area; and
forming a feature pattern from the target layer by transferring the shapes of the first and second positive hardmask patterns to the target layer.
 
9. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a cell array area and a peripheral circuit area;
forming a hardmask structure comprising a plurality of hardmask layers on the target layer in the cell array area and the peripheral circuit area;
forming a photoresist pattern in the cell array area and the peripheral circuit area, the photoresist pattern including a first photoresist pattern in the cell array area and a second photoresist pattern in the peripheral circuit area, the first photoresist pattern and the second photoresist pattern have a different planar shape from each other;
forming a first hard mask pattern in the cell array area and the peripheral circuit area by transferring a shape of the photoresist pattern onto a first hardmask layer that is one of the plurality of hardmask layers, the first hardmask pattern comprising a negative hardmask pattern having first openings in the cell array area and a first positive hardmask pattern having second openings in the peripheral circuit area;
forming a second positive hardmask pattern in the cell array area, the second positive hardmask pattern filling the first openings of the negative hardmask pattern;
removing the negative hardmask pattern in the cell array area; and
forming a feature pattern in the cell array area and the peripheral circuit area by transferring shapes the first and second positive hardmask patterns to the target layer.
 
16. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a cell array area and a peripheral circuit area;
forming a hardmask structure on the target layer in the cell array area and the peripheral circuit area, wherein the hardmask structure includes a first bottom hardmask layer, a second bottom hardmask layer, a main hardmask layer, a reversible hardmask layer, and a top hardmask layer, which are sequentially stacked on the target layer;
forming a photoresist pattern in the cell array area and the peripheral circuit area, the photoresist pattern including a first photoresist pattern in the cell array area and a second photoresist pattern in the peripheral circuit area, the first photoresist pattern including a plurality of holes, the second photoresist pattern including a plurality of first line patterns;
forming a reversible hardmask pattern in the cell array area and the peripheral circuit area by sequentially etching the top hardmask layer and the reversible hardmask layer by using the photoresist pattern as an etching mask in the cell array area and the peripheral circuit area, wherein the reversible hardmask pattern includes a negative hardmask pattern in the cell array area and a first positive hardmask pattern in the peripheral circuit area;
forming a second positive hardmask pattern in the cell array area by filling openings of the negative hardmask pattern in the cell array area;
removing the negative hardmask pattern in the cell array area; and
forming a plurality of island patterns in the cell array area by sequentially etching the main hardmask layer, the second bottom hardmask layer, the first bottom hardmask layer, and the target layer by using the second positive hardmask pattern as an etching mask in the cell array area; and
forming a plurality of second line patterns in the peripheral circuit area by sequentially etching the main hardmask layer, the second bottom hardmask layer, the first bottom hardmask layer, and the target layer by using the first positive hardmask pattern as an etching mask in the peripheral circuit area.