CPC G11C 29/42 (2013.01) [G11C 7/1045 (2013.01); G11C 29/18 (2013.01); G11C 29/44 (2013.01); G11C 2029/1202 (2013.01)] | 24 Claims |
1. An apparatus, comprising:
a memory configured to communicate with a host via at least one data connection and at least one non-data connection, the memory comprising a memory array, the memory array comprising a first portion and a second portion;
the memory further configured to:
receive data from the host via the at least one data connection; and
output the data to the host via the at least one data connection;
the memory further configured to, in a first mode, store and output the data in the first portion and in the second portion of the memory array, the first portion being addressable by a first address, the second portion being addressable by a second address;
the memory further configured to, in a second mode:
receive error-correction code (ECC) of the data from the host, via the at least one non-data connection;
store the data in the first portion of the memory array;
store the ECC of the data in the second portion of the memory array based on the first address; and
output the ECC of the data to the host, via the at least one non-data connection, and
the memory further configured to, in a third mode:
receive the ECC of the data from the host, via the at least one non-data connection;
perform error detection or correction on the data based on the ECC;
store the data, after the error detection or correction, in the first portion and in the second portion of the memory array;
generate the ECC based on the data stored in the first portion and in the second portion of the memory array; and
output the ECC to the host via the at least one non-data connection.
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