US 11,727,994 B2
Performing threshold voltage offset bin selection by package for memory devices
Michael Sheperek, Longmont, CO (US); Kishore Kumar Muchherla, Fremont, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Vamsi Pavan Rayaprolu, San Jose, CA (US); Bruce A. Liikanen, Berthoud, CO (US); and Larry J. Koudele, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 6, 2021, as Appl. No. 17/542,694.
Application 17/542,694 is a continuation of application No. 17/061,713, filed on Oct. 2, 2020, granted, now 11,211,128.
Prior Publication US 2022/0108752 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/20 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/20 (2013.01) [G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
programming a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and
associating the die group with a threshold voltage offset bin.