US 11,727,985 B2
Method of operating resistive memory device to increase read margin
Kwang-woo Lee, Hwaseong-si (KR); Han-bin Noh, Seoul (KR); and Kyu-rie Sim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 7, 2021, as Appl. No. 17/369,211.
Application 17/369,211 is a continuation of application No. 16/390,201, filed on Apr. 22, 2019, granted, now 11,087,840.
Claims priority of application No. 10-2018-0121190 (KR), filed on Oct. 11, 2018.
Prior Publication US 2021/0335422 A1, Oct. 28, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); G11C 11/56 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC G11C 13/0069 (2013.01) [G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); G11C 13/0033 (2013.01); H10B 63/80 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02); G11C 2013/0092 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A resistive memory device comprising:
a memory cell array including a plurality of memory cells, a memory cell comprising a memory element programmable to a plurality of resistance states;
a write circuit configured to program the memory cell to a target resistance state; and
a control circuitry configured to control a write pulse and a post-write pulse to be applied to the memory cell, wherein
the post-write pulse follows the write pulse,
the memory cell is programmed to the target resistance state in response to the write pulse, and
a resistance of the memory cell that is in the target resistance state is increased in response to the post-write pulse,
wherein the post-write pulse is a single pulse having at least n stepped-up voltage levels, n being an integer equal to or more than 2, each of the at least n stepped-up voltage levels having a time period smaller than the write pulse, and
wherein the at least n stepped-up voltage levels have different time periods;
wherein the target resistance state is a resistive state having a relatively high resistance level among 2m resistance states to which the memory cell is programmed, m being a natural number,
wherein the control circuitry is further configured to
control each of the at least n stepped-up voltage levels to increase with a certain amplitude, and
control an n-th stepped-up voltage level of the at least n stepped-up voltage levels of the post-write pulse to be applied to the memory cell such that the n-th stepped-up voltage level is lower than a minimum threshold voltage level of the target resistance state that is changed by an (n−1)-th stepped-up voltage level of the post-write pulse.