CPC G11C 11/4096 (2013.01) [G11C 11/4094 (2013.01); H10B 12/50 (2023.02)] | 20 Claims |
1. A memory device comprising:
a first data line located in a first level of the memory device;
a second data line located in a second level of the memory device;
a memory cell located between the first and second levels and coupled to the first and second data lines, the memory cell including:
a first material located in a third level of the memory device between the first and second levels, the first material forming a memory element of the memory cell;
a second material located in a fourth level of the memory device between the second and third levels, the second material contacting the first material and the second data line; and
a semiconductor material having a p-type material, the semiconductor material extending between the first and second levels and contacting the first and second data lines, and the semiconductor material located adjacent a side of the first material and a side of the second material and separated from the side of each of the first and second materials by an insulator material.
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