US 11,727,983 B2
Single word line gain cell with complementary read write channel
Kamal M. Karda, Boise, ID (US); Haitao Liu, Boise, ID (US); Karthik Sarpatwari, Boise, ID (US); and Durai Vishak Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 21, 2021, as Appl. No. 17/353,090.
Application 17/353,090 is a continuation of application No. 16/722,665, filed on Dec. 20, 2019, granted, now 11,043,260.
Claims priority of provisional application 62/785,163, filed on Dec. 26, 2018.
Prior Publication US 2021/0358538 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4096 (2006.01); G11C 11/4094 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4094 (2013.01); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first data line located in a first level of the memory device;
a second data line located in a second level of the memory device;
a memory cell located between the first and second levels and coupled to the first and second data lines, the memory cell including:
a first material located in a third level of the memory device between the first and second levels, the first material forming a memory element of the memory cell;
a second material located in a fourth level of the memory device between the second and third levels, the second material contacting the first material and the second data line; and
a semiconductor material having a p-type material, the semiconductor material extending between the first and second levels and contacting the first and second data lines, and the semiconductor material located adjacent a side of the first material and a side of the second material and separated from the side of each of the first and second materials by an insulator material.