US 11,727,979 B2
Methods of reducing clock domain crossing timing violations, and related devices and systems
Kallol Mazumder, Boise, ID (US); Navya Sri Sreeram, Boise, ID (US); William C. Waldrop, Boise, ID (US); and Vijayakrishna J. Vankayala, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 7, 2021, as Appl. No. 17/369,055.
Prior Publication US 2023/0007872 A1, Jan. 12, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including a number of memory cells; and
circuitry coupled to the memory array and configured to:
assert an internal signal in response to receipt of a read command or a write command;
cause the internal signal to remain asserted for at least a predetermined time duration including a first time duration for performing an operation associated with the command and an additional time duration; and
generate a command enable signal based on the internal signal and a clock signal, the internal signal and the clock signal being associated with different clock domains.