CPC G11C 11/4076 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a memory array including a number of memory cells; and
circuitry coupled to the memory array and configured to:
assert an internal signal in response to receipt of a read command or a write command;
cause the internal signal to remain asserted for at least a predetermined time duration including a first time duration for performing an operation associated with the command and an additional time duration; and
generate a command enable signal based on the internal signal and a clock signal, the internal signal and the clock signal being associated with different clock domains.
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