US 11,727,893 B2
Active matrix substrate and display device
Yohsuke Fujikawa, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
Filed on Jul. 18, 2022, as Appl. No. 17/866,762.
Application 17/866,762 is a continuation of application No. 17/345,020, filed on Jun. 11, 2021, granted, now 11,423,856.
Application 17/345,020 is a continuation of application No. 16/831,877, filed on Mar. 27, 2020, granted, now 11,049,467, issued on Jun. 29, 2021.
Application 16/831,877 is a continuation of application No. 16/455,830, filed on Jun. 28, 2019, granted, now 10,643,560, issued on May 5, 2020.
Application 16/455,830 is a continuation of application No. 16/059,080, filed on Aug. 9, 2018, granted, now 10,388,238, issued on Aug. 20, 2019.
Application 16/059,080 is a continuation of application No. 15/832,850, filed on Dec. 6, 2017, granted, now 10,083,667, issued on Sep. 25, 2018.
Application 15/832,850 is a continuation of application No. 14/761,349, granted, now 9,870,744, issued on Jan. 16, 2018, previously published as PCT/JP2014/050696, filed on Jan. 16, 2014.
Claims priority of application No. 2013-008254 (JP), filed on Jan. 21, 2013.
Prior Publication US 2022/0351696 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01)
CPC G09G 3/3648 (2013.01) [G02F 1/1345 (2013.01); G02F 1/13452 (2013.01); G02F 1/136286 (2013.01); G09G 2310/0202 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An active matrix substrate comprising:
data lines and scanning lines that are provided in a display region of the active matrix substrate, the data lines and the scanning lines being arranged in a matrix;
switching elements connected to each of the data lines and the scanning lines;
terminals that are provided at a peripheral region of the active matrix substrate to input external signals to the data lines; and
signal lines that are in a line region between the display region and the peripheral region; wherein
one end of each of the signal lines is electrically connected to at least one of the data lines, and another end of each of the signal lines is electrically connected to one of the terminals;
each of the signal lines includes a first line portion provided on a display region side of the signal lines, a second line portion provided on a peripheral region side of the signal lines, and a connection portion that connects the first line portion and the second line portion;
the first line portion and the second line portion of one of the signal lines include a first conductive layer and a second conductive layer, respectively, the first conductive layer and the second conductive layer being different from each other, and the first line portion and the second line portion of another one of the signal lines which is adjacent to the one of the signal lines include the second conductive layer and the first conductive layer, respectively;
the signal lines are divided into a first signal line group and a second signal line group that is close to the first signal line group;
the first line portions of the first signal line group extend in a first direction, and the first line portions of the second signal line group extend in a second direction that is different from the first direction.