US 11,727,882 B2
Pixel and display device
Hanbit Kim, Seoul (KR); Meejae Kang, Suwon-si (KR); Keunwoo Kim, Seongnam-si (KR); Doo-Na Kim, Seongnam-si (KR); Sangsub Kim, Suwon-si (KR); Do Kyeong Lee, Yongin-si (KR); and Jaehwan Chu, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Sep. 29, 2021, as Appl. No. 17/489,399.
Claims priority of application No. 10-2020-0171683 (KR), filed on Dec. 9, 2020.
Prior Publication US 2022/0180811 A1, Jun. 9, 2022
Int. Cl. G09G 3/3258 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3258 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel comprising:
a capacitor electrically connected between a first voltage line and a first node, the first voltage line being configured to receive a first voltage;
a light emitting diode comprising a first electrode electrically connected to a second node, and a second electrode electrically connected to a second voltage line;
a first transistor comprising a first electrode electrically connected to the first voltage line, a second electrode connected to the second node, and a gate electrode electrically connected to the first node;
a second transistor comprising a first electrode connected to a data line, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first scan signal;
a third transistor comprising a first electrode electrically connected to the first node, a second electrode electrically connected to the second node, and a gate electrode configured to receive the first scan signal;
a fourth transistor comprising a first electrode electrically connected to the first node, a second electrode electrically connected to a third voltage line configured to receive a third voltage, and a gate electrode configured to receive a second scan signal; and
a compensation transistor different from the third transistor and forming a current path between the first node and a fourth voltage line configured to receive a compensation voltage, the compensation transistor comprising a first electrode electrically connected to the first node, a second electrode electrically connected to the fourth voltage line, and a gate electrode configured to receive a compensation control voltage.