CPC G06T 1/20 (2013.01) [G06F 9/3877 (2013.01); G06F 9/3891 (2013.01); G06F 9/5077 (2013.01); G06F 16/9027 (2019.01); G06T 15/005 (2013.01); G06T 15/06 (2013.01); G06T 15/10 (2013.01)] | 18 Claims |
1. An apparatus comprising:
memory array to store data for a first set of primitives of a graphics image, the first set of primitives sorted into groups each forming a first level node of a hierarchical acceleration structure;
efficiency analysis circuitry to access the data in the memory array and to evaluate, in parallel, a plurality of potential next-level groupings of the first level nodes to determine an efficiency estimation for each of the plurality of potential next-level groupings in accordance with a dynamically programmable cost or distance function; and
node merging circuitry to merge the first level nodes to form next-level nodes in the hierarchical acceleration structure based on the efficiency estimation for each potential next-level grouping.
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