US 11,727,528 B2
Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array
Michael Doyle, San Jose, CA (US); Travis Schluessler, Berthoud, CO (US); Gabor Liktor, San Francisco, CA (US); Atsuo Kuwahara, Novi, MI (US); and Jefferson Amstutz, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 19, 2022, as Appl. No. 17/724,299.
Application 17/724,299 is a continuation of application No. 17/061,296, filed on Oct. 1, 2020, granted, now 11,315,213.
Application 17/061,296 is a continuation of application No. 16/236,305, filed on Dec. 28, 2018, granted, now 10,832,371, issued on Nov. 10, 2020.
Prior Publication US 2022/0327655 A1, Oct. 13, 2022
Int. Cl. G06T 15/10 (2011.01); G06T 1/20 (2006.01); G06F 16/901 (2019.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06T 15/00 (2011.01); G06T 15/06 (2011.01)
CPC G06T 1/20 (2013.01) [G06F 9/3877 (2013.01); G06F 9/3891 (2013.01); G06F 9/5077 (2013.01); G06F 16/9027 (2019.01); G06T 15/005 (2013.01); G06T 15/06 (2013.01); G06T 15/10 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
memory array to store data for a first set of primitives of a graphics image, the first set of primitives sorted into groups each forming a first level node of a hierarchical acceleration structure;
efficiency analysis circuitry to access the data in the memory array and to evaluate, in parallel, a plurality of potential next-level groupings of the first level nodes to determine an efficiency estimation for each of the plurality of potential next-level groupings in accordance with a dynamically programmable cost or distance function; and
node merging circuitry to merge the first level nodes to form next-level nodes in the hierarchical acceleration structure based on the efficiency estimation for each potential next-level grouping.