US 11,727,260 B2
Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits
Abhishek Sharma, Hillsboro, OR (US); Jack T. Kavalieros, Portland, OR (US); Ian A. Young, Portland, OR (US); Ram Krishnamurthy, Portland, OR (US); Sasikanth Manipatruni, Portland, OR (US); Uygar Avci, Portland, OR (US); Gregory K. Chen, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); Phil Knag, Hillsboro, OR (US); Huseyin Ekin Sumbul, Portland, OR (US); Nazila Haratipour, Hillsboro, OR (US); and Van H. Le, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,828.
Application 17/484,828 is a continuation of application No. 16/147,176, filed on Sep. 28, 2018, granted, now 11,138,499.
Prior Publication US 2022/0012581 A1, Jan. 13, 2022
Int. Cl. G06N 3/063 (2006.01); H01L 27/108 (2006.01); H01L 27/11502 (2017.01); G06N 3/04 (2006.01); G06F 17/16 (2006.01); H01L 27/11 (2006.01); G11C 11/54 (2006.01); G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 11/409 (2006.01); G11C 11/22 (2006.01); G06N 3/065 (2023.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 53/00 (2023.01)
CPC G06N 3/065 (2023.01) [G06F 17/16 (2013.01); G06N 3/04 (2013.01); G11C 7/1006 (2013.01); G11C 7/1039 (2013.01); G11C 11/54 (2013.01); H10B 10/18 (2023.02); H10B 12/01 (2023.02); H10B 12/033 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 53/00 (2023.02); G11C 11/221 (2013.01); G11C 11/409 (2013.01); G11C 11/419 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a network interface;
a peripheral controller;
a main memory; and,
a semiconductor chip having a compute-in-memory (CIM) circuit to implement a neural network, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising a switched capacitor circuit, the switched capacitor circuit comprising a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within metal/dielectric layers of the semiconductor chip.