CPC G06N 3/065 (2023.01) [G06F 17/16 (2013.01); G06N 3/04 (2013.01); G11C 7/1006 (2013.01); G11C 7/1039 (2013.01); G11C 11/54 (2013.01); H10B 10/18 (2023.02); H10B 12/01 (2023.02); H10B 12/033 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 53/00 (2023.02); G11C 11/221 (2013.01); G11C 11/409 (2013.01); G11C 11/419 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
a network interface;
a peripheral controller;
a main memory; and,
a semiconductor chip having a compute-in-memory (CIM) circuit to implement a neural network, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising a switched capacitor circuit, the switched capacitor circuit comprising a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within metal/dielectric layers of the semiconductor chip.
|