US 11,727,258 B2
Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs
Borna J. Obradovic, Leander, TX (US); Titash Rakshit, Austin, TX (US); Rwik Sengupta, Austin, TX (US); Joon Goo Hong, Austin, TX (US); Ryan M. Hatcher, Austin, TX (US); Jorge A. Kittl, Austin, TX (US); and Mark S. Rodder, Dallas, TX (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 7, 2022, as Appl. No. 17/939,807.
Application 17/939,807 is a continuation of application No. 15/806,259, filed on Nov. 7, 2017, granted, now 11,461,620.
Claims priority of provisional application 62/528,856, filed on Jul. 5, 2017.
Prior Publication US 2023/0004789 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01)
CPC G06N 3/063 (2013.01) [H01L 29/40111 (2019.08); H01L 29/42392 (2013.01); H01L 29/785 (2013.01); H01L 29/78391 (2014.09)] 18 Claims
OG exemplary drawing
 
1. A neuromorphic multi-bit digital weight cell configured to store a plurality of potential weights for a neuron in an artificial neural network, the neuromorphic multi-bit digital weight cell comprising:
a parallel cell comprising:
a plurality of passive resistors in parallel; and
a plurality of gating transistors, each gating transistor of the plurality of gating transistors being in series with one passive resistor of the plurality of passive resistors;
a plurality of programming input lines connected to the plurality of gating transistors;
an input terminal connected to the parallel cell; and
an output terminal connected to the parallel cell,
wherein at least one passive resistor of the plurality of passive resistors comprises an un-gated FinFET having an n-doped channel and n+ doped source and drain regions.