CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01)] | 20 Claims |
1. A method of manufacturing a transmission gate, the method comprising:
overlying a first active area with a first metal zero segment, the first active area comprising first and second PMOS transistors;
overlying a second active area with a second metal zero segment, the second active area comprising first and second NMOS transistors; and
configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths, at least one of the conductive paths comprising a first conductive segment perpendicular to the first and second metal zero segments,
wherein the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.
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