US 11,727,186 B2
Automatic identification of hierarchical cells based on selected properties for layout verification
Sridhar Srinivasan, Tualatin, OR (US); Sherif Hany Riad Mohammed Mousa, Beaverton, OR (US); and Padmaja Susarla, McLean, VA (US)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Filed by Siemens Industry Software Inc., Plano, TX (US)
Filed on Apr. 27, 2021, as Appl. No. 17/241,694.
Claims priority of provisional application 63/035,921, filed on Jun. 8, 2020.
Prior Publication US 2021/0383051 A1, Dec. 9, 2021
Int. Cl. G06F 30/398 (2020.01)
CPC G06F 30/398 (2020.01) 17 Claims
OG exemplary drawing
 
1. A method, executed by at least one processor of a computer, comprising:
analyzing a circuit design, circuit components of the circuit design being associated with geometric elements of a layout design, the circuit design using a hierarchical description and comprising circuit blocks, the analyzing comprising identifying electrical properties of circuit blocks in the circuit design, the electrical properties comprising voltage values of input power for a circuit block, current values of input power for a circuit block, a number of devices between power pads of the circuit design and power input ports of a circuit block, or any combination thereof;
classifying instances of each of the circuit blocks into groups of instances based on the electrical properties; and
performing rule checking on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.