US 11,727,178 B2
Under test pin location driven simultaneous signal grouping and pin assignment
Yu Yang, Shanghai (CN); Jianfeng Huang, Shanghai (CN); and Shih-Ying Liu, Hsinchu (TW)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Sep. 29, 2021, as Appl. No. 17/488,908.
Claims priority of provisional application 63/084,801, filed on Sep. 29, 2020.
Prior Publication US 2022/0100942 A1, Mar. 31, 2022
Int. Cl. G06F 30/347 (2020.01)
CPC G06F 30/347 (2020.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin, wherein the channel configuration includes an association of the XDR to a channel;
determining, by a processor, a signal pin channel assignment based on the channel configuration;
updating, by the processor, the channel configuration based on the signal pin channel assignment and a wirelength representative of a total distance between the first signal pin, the second signal pin, and physical ports of the channel; and
performing socket instantiation based on the updated channel configuration and the signal pin channel assignment.