CPC G06F 13/28 (2013.01) [G06F 13/24 (2013.01)] | 20 Claims |
1. A system, comprising:
a plurality of processors, wherein each processor of the plurality of processors is configured to execute program code; and
an integrated circuit coupled to the plurality of processors, wherein the integrated circuit includes:
a direct memory access system configured for multi-processor operation, wherein the direct memory access system includes a plurality of data engines each coupled to a plurality of interfaces via a plurality of switches;
wherein the plurality of switches are programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles specifying addressing information for the plurality of processors;
a plurality of bus endpoints, wherein each bus endpoint of the plurality of bus endpoints is coupled to a processor of the plurality of processors and to a selected switch of the plurality of switches;
a kernel circuit configured for hardware acceleration; and
a network-on-chip coupled to the one or more of the plurality of interfaces of the direct memory access system, the kernel circuit, and at least one bus endpoint of the plurality of bus endpoints, wherein the network-on-chip is programmable to convey packetized data via programmed routes to circuits coupled thereto.
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