US 11,726,929 B2
Operation method of an accelerator and system including the same
Seung Wook Lee, Suwon-si (KR); Soojung Ryu, Seoul (KR); Jintaek Kang, Seoul (KR); and Sunjung Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and SNU R&DB FOUNDATION, Seoul (KR)
Filed on Feb. 2, 2021, as Appl. No. 17/165,018.
Claims priority of application No. 10-2020-0023750 (KR), filed on Feb. 26, 2020.
Prior Publication US 2021/0263865 A1, Aug. 26, 2021
Int. Cl. G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 7/544 (2006.01); G06F 13/28 (2006.01); G06N 3/04 (2023.01); G06N 3/10 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 7/5443 (2013.01); G06F 13/28 (2013.01); G06N 3/04 (2013.01); G06N 3/10 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An operation method of an accelerator, comprising:
receiving one or more workloads assigned by a host controller configured to control the accelerator comprising a plurality of processing elements;
determining, upon the plurality of processing elements performing the workloads, reuse data among data of the workloads, based on at least one of hardware resource information and a memory access cost of the accelerator of a current operation of the one or more workloads; and
providing a result of performing the workloads to the host controller,
wherein the reuse data is data reutilized in a subsequent operation to the current operation of the one or more workloads, and
wherein the at least one of the hardware resource information and the memory access cost is determined through an extension offloaded to a direct memory access (DMA), the DMA is configured to control the data of the workloads input to the multilevel memory comprised in the accelerator or data output from the multilevel memory.