US 11,726,927 B2
Method, apparatus, system for early page granular hints from a PCIe device
Ishwar Agarwal, Portland, OR (US); Rupin H. Vakharwala, Hillsboro, OR (US); Rajesh M. Sankaran, Portland, OR (US); and Stephen R. Van Doren, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 27, 2022, as Appl. No. 17/827,458.
Application 17/827,458 is a continuation of application No. 15/721,777, filed on Sep. 30, 2017, granted, now 11,347,662.
Prior Publication US 2022/0365887 A1, Nov. 17, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 13/42 (2006.01)
CPC G06F 13/161 (2013.01) [G06F 12/0862 (2013.01); G06F 12/1009 (2013.01); G06F 12/1063 (2013.01); G06F 13/1663 (2013.01); G06F 13/4282 (2013.01); G06F 2212/602 (2013.01); G06F 2212/621 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a port, wherein the port is to couple a first device to a second device over an interconnect, and the port comprises protocol circuitry to:
identify attributes of data in memory to be accessed by the first device;
generate an address translation services (ATS) request packet, wherein the ATS request packet comprises a header, the header comprises a transaction hint bit in a first data word of the header and two or more processing hint bits in a fourth data word of the header; and
send the ATS request packet from the first device to the second device, wherein hint information included in the transaction hint bit and the processing hint bits comprise hints for performing cache management at the second device.