CPC G06F 12/0824 (2013.01) [G06F 12/084 (2013.01)] | 20 Claims |
1. A system comprising:
a first die coupleable to a plurality of processing units separate from the first die, the first die implementing a first coherence directory configured to support a first subset of one or more address regions of an address space for the plurality of processing units via a memory controller configured to control access to the first subset of one or more address regions, wherein the memory controller is integrated on an integrated circuit (IC) package separate from the first die.
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