CPC G06F 12/0804 (2013.01) [G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/383 (2013.01); G06F 9/3824 (2013.01); G06F 9/3828 (2013.01); G06F 9/3885 (2013.01); G06F 9/3887 (2013.01); G06F 12/0844 (2013.01); G06F 2212/1032 (2013.01)] | 18 Claims |
1. A method of operating a processor, the method comprising:
receiving object code for an instruction group;
scheduling one or more operations specified in the instruction group to be executed by two or more execution lanes of a processor core; and
executing the scheduled operations by the processor, the executing comprising:
performing a memory operation for a cache line of a data cache, each of plural words of the cache line memory operation being associated with one of the execution lanes of the processor core; and
performing sharding operations for the plural words (a) after loading the words when performing the memory operation, or (b) before storing the words in the data cache when performing the memory operation.
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