US 11,726,912 B2
Coupling wide memory interface to wide write back paths
Douglas C. Burger, Bellevue, WA (US); Aaron L. Smith, Seattle, WA (US); Gagan Gupta, Bellevue, WA (US); and David T. Harper, Seattle, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 29, 2021, as Appl. No. 17/216,563.
Application 17/216,563 is a division of application No. 15/887,640, filed on Feb. 2, 2018, granted, now 10,963,379.
Claims priority of provisional application 62/624,067, filed on Jan. 30, 2018.
Prior Publication US 2021/0216454 A1, Jul. 15, 2021
Int. Cl. G06F 9/30 (2018.01); G06F 12/0804 (2016.01); G06F 9/38 (2018.01); G06F 12/0844 (2016.01)
CPC G06F 12/0804 (2013.01) [G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/383 (2013.01); G06F 9/3824 (2013.01); G06F 9/3828 (2013.01); G06F 9/3885 (2013.01); G06F 9/3887 (2013.01); G06F 12/0844 (2013.01); G06F 2212/1032 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of operating a processor, the method comprising:
receiving object code for an instruction group;
scheduling one or more operations specified in the instruction group to be executed by two or more execution lanes of a processor core; and
executing the scheduled operations by the processor, the executing comprising:
performing a memory operation for a cache line of a data cache, each of plural words of the cache line memory operation being associated with one of the execution lanes of the processor core; and
performing sharding operations for the plural words (a) after loading the words when performing the memory operation, or (b) before storing the words in the data cache when performing the memory operation.