US 11,726,910 B2
Dynamic control of memory bandwidth allocation for a processor
Ian M. Steiner, Portland, OR (US); Andrew J. Herdrich, Hillsboro, OR (US); Wenhui Shu, Shanghai (CN); Ripan Das, Beaverton, OR (US); Dianjun Sun, Shanghai (CN); Nikhil Gupta, Portland, OR (US); and Shruthi Venugopal, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 12, 2020, as Appl. No. 16/816,779.
Claims priority of provisional application 62/817,927, filed on Mar. 13, 2019.
Prior Publication US 2020/0210332 A1, Jul. 2, 2020
Int. Cl. G06F 12/06 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01)
CPC G06F 12/0646 (2013.01) [G06F 11/3037 (2013.01); G06F 11/3495 (2013.01); G06F 2212/1044 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of processor cores;
first circuitry, coupled to the plurality of processor cores, to apply at least one of a plurality of memory bandwidth settings to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by the plurality of processor cores;
a memory controller, coupled to the plurality of processor cores, the memory controller including a performance monitor to generate performance monitoring statistics by monitoring performance of the one or more workloads by the plurality of processor cores based at least in part on performance monitoring configuration parameters; and
second circuitry, coupled to the first circuitry and the memory controller, to set the performance monitoring configuration parameters based at least in part on memory class of service parameters, and to set the memory bandwidth settings based at least in part on the performance monitoring statistics received from the performance monitor.