CPC G06F 12/0646 (2013.01) [G06F 11/3037 (2013.01); G06F 11/3495 (2013.01); G06F 2212/1044 (2013.01)] | 25 Claims |
1. An apparatus comprising:
a plurality of processor cores;
first circuitry, coupled to the plurality of processor cores, to apply at least one of a plurality of memory bandwidth settings to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by the plurality of processor cores;
a memory controller, coupled to the plurality of processor cores, the memory controller including a performance monitor to generate performance monitoring statistics by monitoring performance of the one or more workloads by the plurality of processor cores based at least in part on performance monitoring configuration parameters; and
second circuitry, coupled to the first circuitry and the memory controller, to set the performance monitoring configuration parameters based at least in part on memory class of service parameters, and to set the memory bandwidth settings based at least in part on the performance monitoring statistics received from the performance monitor.
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