US 11,726,909 B2
Two-way interleaving in a three-rank environment
Brett Kenneth Dodds, Boise, ID (US); and Monish Shantilal Shah, Sammamish, WA (US)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jul. 13, 2022, as Appl. No. 17/864,245.
Application 17/864,245 is a continuation of application No. 16/874,998, filed on May 15, 2020, granted, now 11,429,523.
Prior Publication US 2022/0350737 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/06 (2006.01); G06F 9/4401 (2018.01); G06F 12/02 (2006.01); G06F 12/0811 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0607 (2013.01) [G06F 9/4406 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing apparatus comprising:
a three-rank environment comprising a plurality of memory modules, wherein the plurality of memory modules comprises a quantity of memory modules equal to a non-power of two number;
a memory controller operatively coupled with the plurality of memory modules and configured to at least:
load a mapping of target ranges in system memory space interleaved two-ways across locations in the three-rank environment, wherein the target ranges comprise three ranges of rank-agnostic addresses for at least a range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks, and the offsets differ relative to each other for at least one range of the three ranges of rank-agnostic addresses;
receive an instruction to read data at a rank-agnostic location in the system memory space;
using the mapping, map the rank-agnostic location to two interleaved locations offset different amounts from the base location in each of the two ranks mapped to the range of the rank-agnostic location; and
read the data at the two interleaved locations.