CPC G06F 12/0246 (2013.01) [G06F 12/0292 (2013.01); G06F 12/0879 (2013.01); G06F 13/4027 (2013.01); G11C 11/409 (2013.01); G11C 29/42 (2013.01); G11C 29/76 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
an error correction code (ECC) circuit configured to couple to a memory and that includes an arbitration circuit configured to:
receive a memory command directed to the memory, wherein the memory command is associated with a read of or a write of a first unit of data; and
based on the memory command, determine a first data address associated with the first unit of data and a first ECC address associated with first ECC data, wherein:
the first ECC data is associated with the first unit of data and a second unit of data; and
the first data address and the first ECC address are such that, in an address space of the memory:
the first unit of data is followed by the second unit of data, which is followed by the first ECC data;
the first ECC data is adjacent to second ECC data that is associated with a third unit of data; and
the second ECC data is followed by the third unit of data.
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