US 11,726,907 B2
Method and system for in-line ECC protection
Denis Roland Beaudoin, Rowlett, TX (US); Ritesh Dhirajlal Sojitra, Murphy, TX (US); and Samuel Paul Visalli, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 14, 2021, as Appl. No. 17/474,141.
Application 17/474,141 is a continuation of application No. 16/590,515, filed on Oct. 2, 2019, granted, now 11,119,909.
Claims priority of provisional application 62/777,993, filed on Dec. 11, 2018.
Prior Publication US 2021/0406171 A1, Dec. 30, 2021
Int. Cl. G11C 29/00 (2006.01); G06F 12/02 (2006.01); G06F 12/0879 (2016.01); G11C 11/409 (2006.01); G11C 29/42 (2006.01); G06F 13/40 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0292 (2013.01); G06F 12/0879 (2013.01); G06F 13/4027 (2013.01); G11C 11/409 (2013.01); G11C 29/42 (2013.01); G11C 29/76 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an error correction code (ECC) circuit configured to couple to a memory and that includes an arbitration circuit configured to:
receive a memory command directed to the memory, wherein the memory command is associated with a read of or a write of a first unit of data; and
based on the memory command, determine a first data address associated with the first unit of data and a first ECC address associated with first ECC data, wherein:
the first ECC data is associated with the first unit of data and a second unit of data; and
the first data address and the first ECC address are such that, in an address space of the memory:
the first unit of data is followed by the second unit of data, which is followed by the first ECC data;
the first ECC data is adjacent to second ECC data that is associated with a third unit of data; and
the second ECC data is followed by the third unit of data.