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1. A memory system comprising: a memory device including a plurality of super memory blocks; and a memory controller for communicating with the memory device and controlling the memory device, the memory controller comprising a first processor and a second processor, wherein the first processor is configured to manage a main read count table including a plurality of first read count table entries, each one of the plurality of first read count table entries corresponding to one of the plurality of super memory blocks, a first read count table entry comprising information on a count of a first read operation executed on a corresponding super memory block, and the second processor is configured to manage a partial read count table including a plurality of second read count table entries, a second read count table entry including information on a count of a second read operation executed during a recovery operation for an error, when the error occurs during an operation of reading data stored in one of the plurality of super memory blocks, and transmits an update message to the first processor when updating the main read count table based on the partial read count table.
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