US 11,726,876 B2
FPGA acceleration system for MSR codes
Mian Qin, College Station, TX (US); Joo Hwan Lee, San Jose, CA (US); Rekha Pitchumani, Fairfax, CA (US); and Yang Seok Ki, Palo Alto, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 2, 2021, as Appl. No. 17/367,315.
Application 17/367,315 is a continuation of application No. 16/271,777, filed on Feb. 8, 2019, granted, now 11,061,772.
Claims priority of provisional application 62/780,185, filed on Dec. 14, 2018.
Prior Publication US 2021/0334162 A1, Oct. 28, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 13/28 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 13/28 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a host interface circuit configured to receive an offloading instruction from a host processing device configured to manage a storage system, wherein the offloading instruction instructs the apparatus to compute an error correction code associated with data elements stored by the storage system;
a memory interface circuit configured to receive the data elements from the storage system; and
an error code computation circuit configured to compute at least a portion of the error correction code, wherein the error code computation circuit is configurable based upon a number of data nodes associated with the data elements.