| CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/076 (2013.01)] | 20 Claims |
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1. A storage system comprising:
a memory device including a first region including a plurality of single-level cells and a second region different from the first region, the second region including memory cells of a different type than the first region;
error correction circuit configured to detect errors in data; and
a storage controller configured to,
read data from the first region at a first gear level of a plurality of gear levels,
determine an error level of the read data and a current operating state of the memory device, the determining the error level of the read data including comparing a number of errors detected in the read data with a correctable error rate by the error correction circuitry, and
change a gear level of the first region from the first gear level to a second gear level of the plurality of gear levels based on the determined error level of the read data and the determined current operating state of the memory device, and the gear level of the first region being different than a gear level of the second region of the memory device.
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