CPC G06F 11/1048 (2013.01) [G06F 11/108 (2013.01); G06F 11/1044 (2013.01); G06F 11/1441 (2013.01)] | 20 Claims |
14. A memory system comprising:
multiple memory devices; and
a memory controller including processing circuitry having one or more processors, the memory controller configured to perform operations comprising:
arranging multiple parity groups for data protection of data programmed into the multiple memory devices of the memory system, the multiple parity groups arranged in sub-blocks of the memory system, each parity group of the multiple parity groups having multiple data pages in which to write data and having at least one parity page in which to write parity data generated from the data written in the multiple data pages;
writing data to a parity group of the multiple parity groups; and
maintaining a flag in metadata of each data page of the parity group to which the data is written, the flag to identify asynchronous power loss status of previous data pages of the parity group.
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