US 11,726,867 B2
Multi-page parity protection with power loss handling
Harish Reddy Singidi, Fremont, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Xiangang Luo, Fremont, CA (US); Vamsi Pavan Rayaprolu, San Jose, CA (US); and Ashutosh Malshe, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 11, 2022, as Appl. No. 17/741,940.
Application 17/741,940 is a continuation of application No. 16/989,478, filed on Aug. 10, 2020, granted, now 11,334,428.
Application 16/989,478 is a continuation of application No. 16/267,586, filed on Feb. 5, 2019, granted, now 10,747,612.
Claims priority of provisional application 62/786,889, filed on Dec. 31, 2018.
Prior Publication US 2022/0269559 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); G06F 11/14 (2006.01)
CPC G06F 11/1048 (2013.01) [G06F 11/108 (2013.01); G06F 11/1044 (2013.01); G06F 11/1441 (2013.01)] 20 Claims
OG exemplary drawing
 
14. A memory system comprising:
multiple memory devices; and
a memory controller including processing circuitry having one or more processors, the memory controller configured to perform operations comprising:
arranging multiple parity groups for data protection of data programmed into the multiple memory devices of the memory system, the multiple parity groups arranged in sub-blocks of the memory system, each parity group of the multiple parity groups having multiple data pages in which to write data and having at least one parity page in which to write parity data generated from the data written in the multiple data pages;
writing data to a parity group of the multiple parity groups; and
maintaining a flag in metadata of each data page of the parity group to which the data is written, the flag to identify asynchronous power loss status of previous data pages of the parity group.