US 11,726,823 B2
Electronic device having heterogeneous processors and method of processing task using the heterogeneous processors
Hyo Jeong Lee, Seoul (KR); Myeong Jong Kim, Seoul (KR); and Hoon Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 30, 2020, as Appl. No. 17/107,260.
Claims priority of application No. 10-2020-0014043 (KR), filed on Feb. 6, 2020; and application No. 10-2020-0084837 (KR), filed on Jul. 9, 2020.
Prior Publication US 2021/0248011 A1, Aug. 12, 2021
Int. Cl. G06F 9/50 (2006.01); G06F 9/48 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/4881 (2013.01); G06F 2209/5017 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a master processor; and
a plurality of processors operatively coupled to the master processor,
wherein the master processor is configured to process a task including a plurality of subtasks using the plurality of processors,
wherein each of the plurality of processors is assigned to at least one subtask of the plurality of subtasks to process at least one subtask,
wherein the master processor is configured to:
group the plurality of subtasks into a plurality of groups in consideration of execution dependencies among the plurality of subtasks, regardless of which processor of the plurality of processors is to process at least one subtask of the plurality of subtasks;
compare a number of the plurality of groups and a number of the plurality of processors to generate a comparison result;
generate a plurality of worker threads, wherein a number of the plurality of worker threads depends on the comparison result; and
process the plurality of subtasks using the plurality of processors through the plurality of worker threads,
wherein the plurality of processors includes n processors different from each other, n being a natural number of 2 or more,
wherein the n processors are configured to process the plurality of subtasks of the task,
wherein the number of the plurality of worker threads is m, m being a natural number smaller than n, and
wherein the master processor is configured such that IPC (Inter Process Communication) between a master of the master processor and each of the plurality of worker threads occurs 2m times during a time when the plurality of subtasks are processed by the n processors.