US 11,726,812 B2
Dynamic reconfiguration of applications on a multi-processor embedded system
Wilbur William Kaku, Sunnyvale, CA (US); Michael Lyle Purnell, Scotts Valley, CA (US); Geoffrey Neil Ellis, Santa Cruz, CA (US); John Mark Beardslee, Menlo Park, CA (US); Zhong Qing Shang, Cupertino, CA (US); Teng-I Wang, Yorba Linda, CA (US); and Stephen E. Lim, Scotts Valley, CA (US)
Assigned to Coherent Logix, Incorporated, Austin, TX (US)
Filed by Coherent Logix, Incorporated, Austin, TX (US)
Filed on Apr. 29, 2021, as Appl. No. 17/243,890.
Application 17/243,890 is a continuation of application No. 15/976,021, filed on May 10, 2018, granted, now 11,023,272.
Application 15/976,021 is a continuation of application No. 14/921,281, filed on Oct. 23, 2015, granted, now 9,990,227, issued on Jun. 5, 2018.
Application 14/921,281 is a continuation of application No. 13/896,577, filed on May 17, 2013, granted, now 9,195,575, issued on Nov. 24, 2015.
Prior Publication US 2021/0294643 A1, Sep. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/48 (2006.01); G06F 12/00 (2006.01); G06F 9/46 (2006.01); G06F 9/445 (2018.01); G06F 8/656 (2018.01)
CPC G06F 9/4843 (2013.01) [G06F 8/656 (2018.02); G06F 9/445 (2013.01); G06F 9/461 (2013.01); G06F 9/4856 (2013.01); G06F 12/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first subset of a plurality of processors configured to execute a master task;
a second subset of the plurality of processors configured to execute a plurality of applications;
a plurality of memory circuits interspersed among the processors; and
a communication fabric interconnecting the plurality of processors and the plurality of memory circuits, wherein the communication fabric includes a plurality of buffer circuits interspersed among at least a subset of the plurality of processors, wherein the plurality of buffer circuits are configured to communicate data between the plurality of applications executing on the second subset of the plurality of processors via a first set of routes between a first subset of the plurality of buffer circuits;
wherein the first subset of the plurality of processors are configured, in response to executing the master task, to:
initiate storing one or more variable states associated with a first application of the plurality of applications;
initiate swapping the first application with a second application not included in the plurality of applications;
distribute instructions associated with the second application to different ones of the plurality of memory circuits via a second set of routes between a second subset of the plurality of buffer circuits;
execute the second application on the second subset of the plurality of processors; and
initiate restoring the first application by swapping the first application with a third application of the plurality of applications using the one or more variable states.