CPC G06F 9/4843 (2013.01) [G06F 8/656 (2018.02); G06F 9/445 (2013.01); G06F 9/461 (2013.01); G06F 9/4856 (2013.01); G06F 12/00 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a first subset of a plurality of processors configured to execute a master task;
a second subset of the plurality of processors configured to execute a plurality of applications;
a plurality of memory circuits interspersed among the processors; and
a communication fabric interconnecting the plurality of processors and the plurality of memory circuits, wherein the communication fabric includes a plurality of buffer circuits interspersed among at least a subset of the plurality of processors, wherein the plurality of buffer circuits are configured to communicate data between the plurality of applications executing on the second subset of the plurality of processors via a first set of routes between a first subset of the plurality of buffer circuits;
wherein the first subset of the plurality of processors are configured, in response to executing the master task, to:
initiate storing one or more variable states associated with a first application of the plurality of applications;
initiate swapping the first application with a second application not included in the plurality of applications;
distribute instructions associated with the second application to different ones of the plurality of memory circuits via a second set of routes between a second subset of the plurality of buffer circuits;
execute the second application on the second subset of the plurality of processors; and
initiate restoring the first application by swapping the first application with a third application of the plurality of applications using the one or more variable states.
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