US 11,726,811 B2
Parallel context switching for interrupt handling
Yizhou Shan, San Diego, CA (US); Marcos Kawazoe Aguilera, Mountain View, CA (US); Pratap Subrahmanyam, Saratoga, CA (US); and Rajesh Venkatasubramanian, San Jose, CA (US)
Assigned to VMWARE, INC., Palo Alto, CA (US)
Filed by VMware, Inc., Palo Alto, CA (US)
Filed on Jun. 18, 2021, as Appl. No. 17/351,488.
Prior Publication US 2022/0405121 A1, Dec. 22, 2022
Int. Cl. G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/4812 (2013.01) [G06F 9/461 (2013.01); G06F 9/545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a computing device comprising a processor and a memory; and
machine-readable instructions stored in the memory that, when executed by the processor, cause the computing device to at least:
receive an interrupt request during execution of a process in a less privileged mode;
save a current state of the process;
switch from the less privileged mode to a more privileged mode;
process the interrupt request while in the more privileged mode; and
prior to completion of processing the interrupt request:
switch from the more privileged mode to the less privileged mode; and
in parallel to processing the interrupt request, continue execution of the process in the less privileged mode.