US 11,726,793 B2
Data locality enhancement for graphics processing units
Christopher J. Hughes, Santa Clara, CA (US); Prasoonkumar Surti, Folsom, CA (US); Guei-Yuan Lueh, San Jose, CA (US); Adam T. Lake, Portland, OR (US); Jill Boyce, Portland, OR (US); Subramaniam Maiyuran, Gold River, CA (US); Lidong Xu, Beijing (CN); James M. Holland, Folsom, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); Nikos Kaburlasos, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); and Abhishek R. Appu, El Dorado Hills, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 11, 2020, as Appl. No. 17/95,585.
Claims priority of provisional application 62/935,716, filed on Nov. 15, 2019.
Prior Publication US 2021/0149680 A1, May 20, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 12/084 (2016.01); G06T 1/60 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/3891 (2013.01) [G06F 9/5066 (2013.01); G06F 9/544 (2013.01); G06F 12/084 (2013.01); G06T 1/60 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of processing resources including a first processing resource and a second processing resource;
a computer-readable hardware memory communicatively coupled to the first processing resource and the second processing resource; and
a hardware processor to:
receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource; and
move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource based at least in part on an indicator from a context-aware predictor executing on the hardware processor.