US 11,726,783 B2
Filtering micro-operations for a micro-operation cache in a processor
Marko Scrbak, Austin, TX (US); Mahzabeen Islam, Austin, TX (US); John Kalamatianos, Arlington, MA (US); and Jagadish B. Kotra, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Apr. 23, 2020, as Appl. No. 16/856,832.
Prior Publication US 2021/0334098 A1, Oct. 28, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/26 (2006.01); G06F 16/901 (2019.01); G06F 12/0893 (2016.01)
CPC G06F 9/264 (2013.01) [G06F 9/262 (2013.01); G06F 9/3808 (2013.01); G06F 9/3887 (2013.01); G06F 12/0893 (2013.01); G06F 16/9017 (2019.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a processor;
a micro-operation cache in the processor, the micro-operation cache including a plurality of micro-operation cache entries, each micro-operation cache entry configured for storing micro-operations decoded from instruction groups of one or more instructions; and
a micro-operation filter in the processor, the micro-operation filter including a plurality of micro-operation filter table entries, one or more of the micro-operation filter table entries storing identifiers of instruction groups for which the micro-operations are predicted not to be accessed if stored in the micro-operation cache based on the micro-operations having been previously evicted from the micro-operation cache without having been accessed while stored in the micro-operation cache;
wherein the micro-operation filter is configured to:
receive a first identifier for a first instruction group; and
prevent a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.