US 11,726,721 B2
Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system
Byongmo Moon, Seoul (KR); and Jihye Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 18, 2021, as Appl. No. 17/405,753.
Claims priority of application No. 10-2020-0115516 (KR), filed on Sep. 9, 2020; and application No. 10-2021-0004928 (KR), filed on Jan. 13, 2021.
Prior Publication US 2022/0075564 A1, Mar. 10, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 7/22 (2006.01); H01L 25/065 (2023.01)
CPC G06F 3/0673 (2013.01) [G11C 7/222 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature, and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature; and
a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value in an initialization process of the memory device or in a test process for the memory device,
wherein the memory device includes a temperature sensor configured to sense a range of temperatures, including the first temperature and the second temperature, of the memory device, and
wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a sensed temperature of the memory device and the weight.