CPC G06F 3/0656 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
12. A storage device, comprising:
a memory device including a plurality of sequential areas and a random area other than the plurality of sequential areas, the plurality of sequential areas storing pieces of data corresponding to consecutive logical addresses input from a host; and
a memory controller configured to receive a write request from the host and control the memory device so that sub-data of write data corresponding to the write request is stored in the random area when dummy data has been stored in a sequential area among the plurality of sequential areas,
wherein the sequential area corresponds to a logical address included in the write request, and
wherein a size of the sub-data corresponds to a size of the dummy data.
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