| CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |
|
1. A semiconductor device comprising:
a first chip electrically connected to a terminal to which a signal from a host is input;
a second chip to which the first chip is electrically connected; and
a third chip to which the first chip is electrically connected in parallel with the second chip,
wherein the first chip includes:
a first buffer memory corresponding to the second chip; and
a second buffer memory corresponding to the third chip,
the second chip includes a third buffer memory,
the third chip includes a fourth buffer memory,
a capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory, and
a capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory,
wherein each of the second chip and the third chip is a memory chip, and
the first chip is configured to:
receive a first request from the host,
issue a first command to the second chip based on the received first request,
receive a second request from the host after receiving the first request, and
issue a second command to the third chip based on the received second request after issuing the first command,
the second chip is configured to:
read first data based on the first command; and
transmit the read first data to the first chip,
the third chip is configured to:
read second data based on the second command; and
transmit the read second data to the first chip, and wherein
the first chip is configured to
perform, in parallel with a first operation of storing the first data received from the second chip into the first buffer memory, a second operation of transmitting the first data from the first buffer memory to the host.
|