US 11,726,703 B2
Extending size of memory unit
Sanjay Subbarao, Irvine, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,023.
Application 17/871,023 is a continuation of application No. 17/179,059, filed on Feb. 18, 2021, granted, now 11,409,461.
Prior Publication US 2022/0357872 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operably coupled to the memory device, configured to perform operations comprising:
processing a request, from a host system, to read stored data from a first memory address, the first memory address corresponding to a first memory location on the memory device, the processing of the request comprising:
accessing a truncated version of a first memory unit from the first memory location, the truncated version of the first memory unit comprising a first portion of first protection data for a non-truncated version of the first memory unit and excluding a second portion of first protection data for the non-truncated version of the first memory unit;
performing an error-correction process on the truncated version of the first memory unit based on the first portion of first protection data, the truncated version of the first memory unit comprising a first portion of first protection data for a non-truncated version of the first memory unit and excluding a second portion of first protection data for the non-truncated version of the first memory unit, the error-correction process being performed on the truncated version of the first memory unit based on the first portion of protection data;
determining whether the error-correction process performed on the truncated version of the first memory unit triggers an error-correction failure; and
in response to determining that the error-correction process performed on the truncated version of the first memory unit triggers the error-correction failure, performing the error-correction process on a non-truncated version of the first memory unit, the non-truncated version of the first memory unit being generated by combining the truncated version of the first memory unit, accessed from the first memory location, with the second portion of first protection data accessed from a different memory unit of the memory device.