US 11,726,670 B2
Methods of operating memory controllers, memory controllers performing the methods and memory systems including the memory controllers
Sungrae Kim, Seoul (KR); Sunghye Cho, Hwaseong-si (KR); Kijun Lee, Seoul (KR); and Myungkyu Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 25, 2022, as Appl. No. 17/704,354.
Claims priority of application No. 10-2021-0085267 (KR), filed on Jun. 30, 2021.
Prior Publication US 2023/0004308 A1, Jan. 5, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a memory controller configured to control a memory module, the memory module including a plurality of data chips and at least one parity chip, each of the data chips and the at least one parity chip including an on-die error correction code (ECC) engine, the method comprising:
receiving a decoding status flag from the memory module;
obtaining a first number and a second number based on the decoding status flag, the first number representing a number of first chips including an uncorrectable error that is uncorrectable by the respective on-die ECC engine, the second number representing a number of second chips including a correctable error that is correctable by the respective on-die ECC engine;
selecting at least one of a plurality of decoding schemes based on at least one of the first number and the second number; and
performing, by a system ECC engine included in the memory controller, an ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.