| CPC G06F 3/0619 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A memory controller for encoding additional data in a memory and retaining a number of error correction code bits used by the memory, the memory controller comprising:
a host interface;
an error correction encoder; and
an error correction decoder,
wherein the memory controller is configured to:
receive a write request to write a data payload to the memory comprising a plurality of memory devices, the data payload including data and metadata associated with the data;
in response to the write request:
generate a checksum computed over the data payload;
generate error correction code data computed over the data, the metadata, and the checksum; and
store the data and the error correction code data without the metadata and without the checksum across the plurality of memory devices;
receive a read request to read the data payload from the memory; and
in response to receiving the read request:
retrieve the data and the error correction code data from the memory; and
perform erasure decoding on the data and the error correction code data to obtain the metadata and the checksum, and
wherein the data retrieved from the memory includes errors that are uncorrectable by error decoding, and wherein the memory controller is further configured to perform error recovery attempt operations including:
selecting a memory device from the plurality of memory devices;
processing the errors as erasures at locations in the selected memory device by performing erasure decoding using the error correction code data to obtain speculative data;
computing a verification checksum over the speculative data and the metadata; and
determining whether the checksum corresponds to the verification checksum.
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