US 11,726,373 B2
Semiconductor device and display device
Hajime Kimura, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd.
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Oct. 24, 2022, as Appl. No. 17/972,144.
Application 17/972,144 is a continuation of application No. 17/128,531, filed on Dec. 21, 2020, granted, now 11,520,193.
Application 17/128,531 is a continuation of application No. 16/227,360, filed on Dec. 20, 2018, granted, now 10,877,329, issued on Dec. 29, 2020.
Application 16/227,360 is a continuation of application No. 15/229,838, filed on Aug. 5, 2016, granted, now 10,162,235, issued on Dec. 25, 2018.
Application 15/229,838 is a continuation of application No. 13/600,658, filed on Aug. 31, 2012, granted, now 9,411,203, issued on Aug. 9, 2016.
Application 13/600,658 is a continuation of application No. 12/765,084, filed on Apr. 22, 2010, granted, now 8,259,463, issued on Sep. 4, 2012.
Application 12/765,084 is a continuation of application No. 11/405,327, filed on Apr. 17, 2006, granted, now 7,710,739, issued on May 4, 2010.
Claims priority of application No. 2005-133741 (JP), filed on Apr. 28, 2005.
Prior Publication US 2023/0046143 A1, Feb. 16, 2023
Int. Cl. G02F 1/1345 (2006.01); G09G 3/20 (2006.01); H05K 1/11 (2006.01); H05K 3/36 (2006.01); G02F 1/133 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1339 (2006.01); G02F 1/1341 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); H05K 1/14 (2006.01); H05K 1/02 (2006.01); G09G 3/36 (2006.01)
CPC G02F 1/13452 (2013.01) [G02F 1/1339 (2013.01); G02F 1/1341 (2013.01); G02F 1/1368 (2013.01); G02F 1/13306 (2013.01); G02F 1/13394 (2013.01); G02F 1/133345 (2013.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G09G 3/20 (2013.01); G09G 3/2092 (2013.01); H01L 27/1222 (2013.01); H05K 1/117 (2013.01); H05K 1/148 (2013.01); H05K 3/361 (2013.01); G09G 3/3614 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/08 (2013.01); G09G 2310/0264 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); G09G 2330/08 (2013.01); H01L 2924/0002 (2013.01); H05K 1/0263 (2013.01); H05K 1/0265 (2013.01); H05K 2201/094 (2013.01); H05K 2201/09727 (2013.01); H05K 2201/10136 (2013.01); H05K 2201/10166 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a sealing material;
a plurality of scan line driver circuits;
a connection terminal portion, comprising a plurality of connection pads, over a first substrate;
a plurality of wirings electrically connected to each of the plurality of connection pads; and
a pixel portion including a transistor and a display element, the transistor comprising:
a gate electrode over the first substrate;
a semiconductor layer over and overlapping with the gate electrode; and
a first conductive layer and a second conductive layer electrically connected to the semiconductor layer,
wherein the second conductive layer is electrically connected to a first pixel electrode of the display element,
wherein a color filter overlapping with the display element is provided on the first substrate side,
wherein a spacer is provided over the color filter and the first pixel electrode,
wherein the plurality of connection pads have a similar width,
wherein the plurality of wirings are arranged at substantially regular intervals,
wherein the plurality of scan line driver circuits is provided over the first substrate,
wherein the sealing material surrounds the pixel portion and the plurality of scan line driver circuits,
wherein the sealing material does not surround the plurality of connection pads,
wherein the plurality of wirings comprises a first region not overlapping the sealing material,
wherein the plurality of wirings comprises a second region overlapping the sealing material,
wherein the first conductive layer and the second conductive layer comprise copper,
wherein the first substrate comprises glass,
wherein the gate electrode comprises copper,
wherein the first pixel electrode comprises indium, tin, and oxygen, and
wherein the semiconductor layer comprises amorphous silicon.