US 11,726,142 B2
Integrated circuit self-repair method and integrated circuit thereof
Yu-Pin Lin, Hsinchu (TW); and Lien-Hsiang Sung, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Sep. 23, 2020, as Appl. No. 17/30,069.
Claims priority of application No. 109124653 (TW), filed on Jul. 21, 2020.
Prior Publication US 2022/0026489 A1, Jan. 27, 2022
Int. Cl. G01R 31/3187 (2006.01); G11C 29/44 (2006.01); G11C 29/14 (2006.01); G11C 13/00 (2006.01); G11C 11/406 (2006.01); G06F 11/14 (2006.01); G06F 11/00 (2006.01); G11C 16/34 (2006.01); G11C 5/14 (2006.01)
CPC G01R 31/3187 (2013.01) [G11C 29/14 (2013.01); G11C 29/4401 (2013.01); G06F 11/002 (2013.01); G06F 11/1441 (2013.01); G11C 5/148 (2013.01); G11C 11/40618 (2013.01); G11C 11/40622 (2013.01); G11C 13/0033 (2013.01); G11C 16/3418 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit self-repair method, comprising:
transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state;
outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and
when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state;
wherein the main register transmits a multi-bit logic state to an encoding unit, the encoding unit converts the multi-bit logic state into a plurality of predetermined logic states and transmits the predetermined logic states to the corresponding registers, so that the registers output the predetermined logic states to a decoding unit to combine the predetermined logic states into the multi-bit logic state to drive the controlled circuit to perform the function.