CPC G01R 31/31724 (2013.01) [G01R 31/3177 (2013.01); G01R 31/3187 (2013.01); G01R 31/31813 (2013.01); G01R 31/318555 (2013.01); G06F 11/1417 (2013.01); G06F 11/2268 (2013.01); G06F 11/2273 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 11/273 (2013.01); G06F 11/3688 (2013.01)] | 20 Claims |
1. A system comprising:
one or more interfaces that receives test patterns for in-system testing of a chip of an autonomous machine; and
a processor to control the in-system testing by updating components of the in-system testing while the chip is being used to execute one or more processes for the autonomous machine, wherein the components of the in-system testing include at least one application sequence, one or more targeted fault modes, and one or more test conditions.
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