US 11,726,139 B2
In-system test of chips in functional systems
Shantanu Sarangi, Santa Clara, CA (US); Jae Wu, Santa Clara, CA (US); Andi Skende, Santa Clara, CA (US); and Rajith Mavila, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Aug. 8, 2022, as Appl. No. 17/883,199.
Application 17/883,199 is a continuation of application No. 16/230,929, filed on Dec. 21, 2018, granted, now 11,408,934.
Claims priority of provisional application 62/609,775, filed on Dec. 22, 2017.
Prior Publication US 2022/0382659 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/317 (2006.01); G01R 31/3187 (2006.01); G01R 31/3177 (2006.01); G06F 11/14 (2006.01); G06F 11/36 (2006.01); G06F 11/27 (2006.01); G06F 11/22 (2006.01); G01R 31/3181 (2006.01); G06F 11/267 (2006.01); G01R 31/3185 (2006.01); G06F 11/273 (2006.01)
CPC G01R 31/31724 (2013.01) [G01R 31/3177 (2013.01); G01R 31/3187 (2013.01); G01R 31/31813 (2013.01); G01R 31/318555 (2013.01); G06F 11/1417 (2013.01); G06F 11/2268 (2013.01); G06F 11/2273 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 11/273 (2013.01); G06F 11/3688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
one or more interfaces that receives test patterns for in-system testing of a chip of an autonomous machine; and
a processor to control the in-system testing by updating components of the in-system testing while the chip is being used to execute one or more processes for the autonomous machine, wherein the components of the in-system testing include at least one application sequence, one or more targeted fault modes, and one or more test conditions.