US 11,723,294 B2
Memory device and method for fabricating the same
Hsia-Wei Chen, Taipei (TW); Chih-Hung Pan, Taichung (TW); Chih-Hsiang Chang, Taichung (TW); Yu-Wen Liao, New Taipei (TW); and Wen-Ting Chu, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 25, 2020, as Appl. No. 16/912,341.
Prior Publication US 2021/0408373 A1, Dec. 30, 2021
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8416 (2023.02) [H10N 70/023 (2023.02); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a memory device, comprising:
forming a bottom electrode via in a dielectric layer over a substrate;
depositing a bottom electrode layer over the substrate, wherein the bottom electrode layer comprises a non-noble metal layer and a noble metal layer over the non-noble metal layer, and each of the non-noble metal layer and the noble metal layer comprises a first portion over the bottom electrode via and a second portion over the dielectric layer;
depositing a buffer layer over the first and second portions of the noble metal layer of the bottom electrode layer;
performing a surface treatment to a top surface of the buffer layer;
depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment;
forming a top electrode over the resistance switch layer; and
patterning the resistance switch layer into a resistance switch element below the top electrode.