US 11,723,290 B2
Semiconductor device including data storage structure
Kyung Hwan Lee, Suwon-si (KR); Yong Seok Kim, Suwon-si (KR); Tae Hun Kim, Suwon-si (KR); Seok Han Park, Suwon-si (KR); Satoru Yamada, Suwon-si (KR); and Jae Ho Hong, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 29, 2021, as Appl. No. 17/514,086.
Application 17/514,086 is a continuation of application No. 16/592,041, filed on Oct. 3, 2019, granted, now 11,165,018.
Claims priority of application No. 10-2019-0110620 (KR), filed on Sep. 6, 2019.
Prior Publication US 2022/0052257 A1, Feb. 17, 2022
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/24 (2023.02) [H10B 63/34 (2023.02); H10N 70/023 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a lower structure including an impurity region;
a stack structure on the lower structure;
separation structures penetrating the stack structure on the lower structure;
an opening penetrating the stack structure between the separation structures;
a vertical structure in the opening;
a contact plug electrically connected to the vertical structure on the stack structure; and
a bit line electrically connected to the contact plug on the contact plug,
wherein the stack structure includes interlayer insulating layers and gate electrodes in contact with each other and alternately layered,
wherein the vertical structure includes:
a core region having insulating properties and spaced apart from a side wall of the opening,
a semiconductor layer covering a side surface and a lower surface of the core region,
a gate dielectric layer between an external side surface of the semiconductor layer and the gate electrodes,
a data storage structure interposed between the core region and the semiconductor layer, and covering the side surface and the lower surface of the core region, and
a pad pattern in contact with an upper surface of the core region,
wherein an upper end of the data storage structure overlaps the pad pattern,
wherein the impurity region and the pad pattern include a doped silicon having N-type conductivity,
wherein the contact plug is in contact with the pad pattern, and
wherein the data storage structure includes a variable resistive material layer having an oxygen vacancy.