US 11,723,289 B2
Variable resistance memory device
Seyun Kim, Seoul (KR); Jinhong Kim, Seoul (KR); Soichiro Mizusaki, Suwon-si (KR); Jungho Yoon, Yongin-si (KR); and Youngjin Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 15, 2020, as Appl. No. 16/875,119.
Claims priority of application No. 10-2019-0176731 (KR), filed on Dec. 27, 2019.
Prior Publication US 2021/0202833 A1, Jul. 1, 2021
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/80 (2023.02); H10N 70/8833 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A variable resistance memory device comprising:
a variable resistance layer including a first layer, a second layer, and a third layer,
the second layer on the first layer,
the first layer including a first material,
the second layer including a second material having a valence different from a valence of the first material
the third layer on the second layer, the third layer including a third material having a valence different from a valence of the second material;
wherein each of the first layer, the second layer, and the third layer have a thickness of 10 nm or less; and
a first conductive element and a second conductive element on the variable resistance layer and separated from each other so that an electric current path is formed in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.