US 11,723,285 B2
Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same
Sanghoon Ahn, Suwon-si (KR); Oik Kwon, Suwon-si (KR); Jeonghee Park, Suwon-si (KR); and Kihyun Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 21, 2022, as Appl. No. 17/655,589.
Application 17/655,589 is a continuation of application No. 16/589,456, filed on Oct. 1, 2019, granted, now 11,296,277.
Claims priority of provisional application 62/746,220, filed on Oct. 16, 2018.
Claims priority of application No. 10-2019-0037630 (KR), filed on Apr. 1, 2019; and application No. 10-2019-0060777 (KR), filed on May 23, 2019.
Prior Publication US 2022/0209103 A1, Jun. 30, 2022
Int. Cl. H10N 50/10 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/85 (2023.01); H10N 70/00 (2023.01)
CPC H10N 50/10 (2023.02) [H10B 61/00 (2023.02); H10B 63/80 (2023.02); H10N 50/01 (2023.02); H10N 50/85 (2023.02); H10N 70/063 (2023.02); H10N 70/068 (2023.02); H10N 70/841 (2023.02); H10N 70/882 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a variable resistance memory device, comprising:
forming a plurality of first conductive lines with an insulating pattern disposed between neighboring first conductive lines of the plurality of first conductive lines;
forming a stacked structure comprising a lower electrode layer, a variable resistance layer, and an upper electrode layer, which are sequentially stacked on the plurality of first conductive lines and the insulating pattern;
etching the stacked structure to form a plurality of memory cells, each comprising a lower electrode, a variable resistor, and an upper electrode;
forming an anti-oxidation layer covering the lower electrode, the variable resistor, and the upper electrode of the plurality of memory cells;
forming a capping layer covering the anti-oxidation layer; and
forming an interlayer insulating layer which fills a space between neighboring memory cells of the plurality of memory cells,
wherein the anti-oxidation layer includes SiCxHy.