US 11,723,284 B2
Top-interconnection metal lines for a memory array device and methods for forming the same
Yu-Feng Yin, Hsinchu (TW); Tai-Yen Peng, Hsinchu (TW); An-Shen Chang, Jubei (TW); Han-Ting Tsai, Kaoshiung (TW); Qiang Fu, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 7, 2021, as Appl. No. 17/224,309.
Claims priority of provisional application 63/039,529, filed on Jun. 16, 2020.
Prior Publication US 2021/0391532 A1, Dec. 16, 2021
Int. Cl. H10N 50/10 (2023.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/10 (2023.02) [H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory array device, comprising:
an array of memory cells located over a substrate, wherein each of the memory cells comprises, from bottom to top, a bottom electrode, a memory element, and a top electrode;
a memory-level dielectric layer laterally surrounding the array of memory cells, wherein top surfaces of the top electrodes are located within a horizontal plane including a top surface of the memory-level dielectric layer;
top-interconnection metal lines laterally extending along a horizontal direction, wherein each of the top-interconnection metal lines contacts, or incorporates, a respective row of top electrodes;
an upper-level etch stop dielectric layer contacting a top surface of the memory-level dielectric layer and laterally surrounding the top-interconnection metal lines;
a dielectric matrix layer laterally surrounding the top-interconnection metal lines and having a top surface within a horizontal plane including top surface of the top-interconnection metal lines; and
a cap-level etch stop dielectric layer overlying the top-interconnection metal lines and having sidewalls that are vertically coincident with sidewalls of the dielectric matrix layer.