US 11,723,247 B2
Display device
Soon Dong Kim, Yongin-si (KR); and Jin Wook Yang, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Appl. No. 17/263,533
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
PCT Filed Feb. 8, 2019, PCT No. PCT/KR2019/001596
§ 371(c)(1), (2) Date Jan. 26, 2021,
PCT Pub. No. WO2020/032336, PCT Pub. Date Feb. 13, 2020.
Claims priority of application No. 10-2018-0092364 (KR), filed on Aug. 8, 2018.
Prior Publication US 2021/0175318 A1, Jun. 10, 2021
Int. Cl. H10K 59/131 (2023.01); G09G 3/3233 (2016.01)
CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0202 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A display device, comprising:
a plurality of data lines to supply data signals;
a plurality of pixels each comprising a light-emitting element, a first transistor to control current flowing through the light-emitting element, a second transistor connected between the first transistor and one of the plurality of data lines, a third transistor connected between a second electrode and a gate electrode of the first transistor, a fourth transistor connected between a first electrode of the third transistor and an initialization power source, and an initialization transistor connected between the initialization power source and a first electrode of the light-emitting element, each of the first transistor, the second transistor, the third transistor, the fourth transistor and the initialization transistor comprising a semiconductor pattern; and
a conductive pattern disposed on and connected to the second transistor through a first contact hole,
wherein the data line is disposed on a layer different from that of the conductive pattern, and is connected to the conductive pattern through a second contact hole,
wherein the first contact hole and the second contact hole overlap each other, when viewed on a plane,
wherein the data line and the conductive pattern overlap the semiconductor pattern of the second transistor without overlapping the semiconductor pattern of each of the fourth transistor and the initialization transistor,
wherein each of the plurality of data lines comprises a first sub data line extending in a first direction and a second sub data line extending in the first direction,
wherein the first sub data line and the second sub data line are provided on both sides of a pixel column in which at least two or more of the plurality of pixels are arranged in the first direction,
wherein one of the pixels of the pixel column is connected to the first sub data line, and another one of the pixels of the pixel column adjacent to the one of the pixels connected to the first sub data line is connected to the second sub data line,
wherein each of the pixels of the pixel column is connected to one of the first sub data line and the second sub data line, and
wherein an active pattern of the second transistor does not overlap the conductive pattern.