US 11,723,220 B2
Strained transistors and phase change memory
Remy Berthelon, Saint Martin d'Heres (FR); and Olivier Weber, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Apr. 29, 2021, as Appl. No. 17/244,514.
Claims priority of application No. 2004330 (FR), filed on Apr. 30, 2020.
Prior Publication US 2021/0343788 A1, Nov. 4, 2021
Int. Cl. H10B 63/00 (2023.01)
CPC H10B 63/32 (2023.02) [H10B 63/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing an electronic chip, comprising:
oxidizing a plurality of first portions and a plurality of second portions of a semiconductor layer down to an insulator, the insulator covering a semiconductor substrate, the semiconductor layer disposed on the insulator;
generating stresses in third portions of the semiconductor layer, each of the third portions extending between two portions of any of the first or second portions of the semiconductor layer; and
forming cavities extending at least to the substrate through the second portions and the insulator.