CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
1. A semiconductor structure, comprising:
a memory region;
a logic region adjacent to the memory region;
a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region;
a carbon-based layer over the memory region, wherein the carbon-based layer comprises a recess between the first MTJ cell and the second MTJ cell; and
a bottom electrode via under the first MTJ cell, wherein an uppermost surface of the bottom electrode via is above an uppermost surface of the carbon-based layer.
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