US 11,723,213 B2
Method and structures pertaining to improved ferroelectric random-access memory (FeRAM)
Tzu-Yu Chen, Kaohsiung (TW); Kuo-Chi Tu, Hsin-Chu (TW); Sheng-Hung Shih, Hsinchu (TW); and Fu-Chen Chang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 15, 2021, as Appl. No. 17/376,531.
Application 17/376,531 is a continuation in part of application No. 16/452,965, filed on Jun. 26, 2019, granted, now 11,195,840.
Claims priority of provisional application 62/738,604, filed on Sep. 28, 2018.
Prior Publication US 2021/0343731 A1, Nov. 4, 2021
Int. Cl. H10B 53/30 (2023.01); H01L 49/02 (2006.01)
CPC H10B 53/30 (2023.02) [H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
14. An integrated circuit, comprising:
a semiconductor substrate;
an interconnect structure disposed over an upper surface of the semiconductor substrate, the interconnect structure comprising: a bottommost metal layer, a plurality of inter-metal layers disposed at different heights over the bottommost metal layer, and a plurality of top metal layers disposed at different heights over the inter-metal layers, and a bond pad layer disposed over the plurality of top metal layers; wherein each of the plurality of top metal layers has a width and a thickness that is greater than a width and a thickness, respectively, of each of the plurality of inter-metal layers; and
a ferroelectric capacitor structure disposed within the interconnect structure, the ferroelectric capacitor structure comprising: a bottom electrode structure disposed over an uppermost inter-metal layer of the plurality of inter-metal layers, a ferroelectric structure over the bottom electrode structure, and a top electrode structure disposed under a lowermost top metal layer of the plurality of top metal layers.